PA communication chip board
Description
FBC0409 is a fieldbus interface and controller IC which conforms to IEC 61158 filedbus physical layer definition. It supports typical embedded CPU and MCU, and satisfies the demands of high performance fieldbus masters or slavers.
FBC0409 contains Manchester data encoder and decoder on chip. It requires a medium interface and external filter for connection to a fieldbus system, and can automatically correct bus polarity. FBC0409 also contains 4k bytes embedded data RAM, applying DMA controller. The implementation of message transmission and address resolution can be executed without CPU intervention. The Rx and Tx data status is available in status registers of FBC0409, such as status of line operation, code error, frame loss, frame collision.
FBC0409 implement a portion of data-link layer function. Tx/Rx frame check sequence (FCS), 16 bits 1ms timer, 16 bits 1/32ms timer, 16 bits octet time timer, frame code decoding and address resolution.
|
NAME |
TYPE |
DEFINITION |
NOTE |
|
PB_ADDR[11: 0] |
INPUT |
12 Bits Address Bus |
|
|
PB_DATA[7: 0] |
INOUT |
8 Bits Data Bus |
|
|
PB_RAMCS_N |
INPUT |
Internal SRAM Selection, Active Low |
|
|
PB_REGCS_N |
INPUT |
Register Chip Select, Active Low |
|
|
RST_N |
INPUT |
System Reset, Active Low |
|
|
PB_WR |
INPUT |
CPU Write Control |
|
|
PB_READY |
INPUT |
CPU Read Control |
|
|
SCLK |
INPUT |
System Clock, Same Source as CPU |
|
|
NCLK |
INPUT |
Line Clock, Independent of SCLK |
|
|
PO_CLK125K |
OUTPUT |
125k Time Clock Output |
|
|
PO_RDY |
OUTPUT |
CPU Delay Request, PO_READY Will Active when CPU Access Internal SRAM Which is Busy |
0 or HiZ |
|
PBO_INT_N |
OUTPUT |
Interrupt Request to CPU, Active Low |
|
|
PBI_INT_N |
INPUT |
Interrupt Input From Outside, Active Low |
|
|
TXEN |
OUTPUT |
Fieldbus Active Indication, its Level is Decided by Software |
|
|
TX_FFD |
OUTPUT |
Fieldbus Data Output |
|
|
RX_FFD |
INPUT |
Fieldbus Bus Data Input |
|
|
VDD |
POWER |
Power Supply |
|
|
VSS |
GND |
Ground |
|
Features
FBC0409 is designed for fieldbus physical and part data link communication functions, details list below:
Supports line data rate 31.25K Bit/S
Build-in Manchester Encoder/Decoder
Transmitter Jibber inhibit, receiver super long frame inhibit
Automatic parity recognize and correct
Message type and destination address detection automatically
Automatic transmitter and receiver frame check
Build-in three channels DMA controller，used to control data transmitting, receiving and address recognization looking up table memory management
4k bytes asynchronous SRAM internal as communication buffer for transmitting, receiving and address lookup table memory
Length of Preamble, Start and Stop delimiter under software controlled
Build-in bus arbiter, CPU accessing internal SRAM correctly
Data link layer timer ( 1ms、1/32 ms、octet time timer )
Designed lots of useful interrupt and status Registers
Compatibility with INTEL、ARM serials CPU
Internal loop back for test
STANDBY feature
Power supply: 2.7～5.5V
Power consumption: <600uA </span>
Operating temperature range: -40℃～85℃
Available in 44-pins TQFP package
Designed to comply with IEC 61158-2
Supports line data rate 31.2Skbit/s
Good at integration, simple external circuit, small size
Available in 44-pin TQFP package
Low power consumption design : <600µA</span>
Performance Characteristic
Supports line data rate 31.25K BIT/S
Build-in Manchester Encoder/Decoder
Transmitter Jibber inhibit, receiver super long frame inhibit
Automatic parity recognition and correction
Build-in two channels DMA controller，used to control data transmitting, receiving and address recognition
Build-in bus arbiter, CPU accessing internal SRAM correctly
Internal loop back for test
Operating temperature：-40℃～85℃
Typical Application
Chip FBC0409 was designed as fieldbus communication controller, following is its typical application.
Contact : Yvette Jiang, +86 18304037682
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